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for free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. for small orders, phone 1-800-835-8769. general description the max3831/max3832 are 4:1 multiplexers (muxes) and 1:4 demultiplexers (demuxes) with automatic chan- nel assignment. operating from a single +3.3v supply, the mux receives four parallel, 622mbps sdh/sonet channels. these channels are bit interleaved to gener- ate a serial data stream of 2.488gbps for interfacing to an optical or an electrical driver. a 10-bit-wide elastic buffer tolerates up to ?.5ns skew between any parallel data input and the reference clock. an external 155mhz reference clock is required for the on-chip pll to synthesize a high-frequency 2.488ghz clock for tim- ing the outgoing data streams. the max3831/max3832? demux receives 2.488gbps serial data and the 2.488ghz clock from an external clock/data recovery device (max3876), converting it to four 622mbps lvds outputs. the max3831 provides a 622mhz lvds clock output, and the max3832 pro- vides a 155mhz lvds clock output. an internal frame detector looks for a 622mbps sdh/sonet framing pat- tern and rolls the demux to maintain proper channel assignment at the outputs. these devices also include an embedded pattern gen- erator that enables a full-speed, built-in self-test (bist). two different loopback modes provide system test flexi- bility. a ttl loss-of-frame monitor is included. the max3831/max3832 are available in 64-pin tqfp-ep (exposed paddle) packages and are specified over the upper commercial (0? to +85?) temperature range. features +3.3v single supply 1.45w power dissipation (max3831) 4-channel mux/demux with fully integrated 2.488ghz clock generator frame detection maintains channel assignment 7.5ns elastic store range 2.5ps rms serial-data output random jitter 8ps serial-data output deterministic jitter 622mbps lvds parallel input/output 2.488gbps serial cml input/output on-chip pattern generator provides high-speed bist system test flexibility: system loopback, line loopback loss-of-frame indicator applications sdh/sonet backplanes atm switching networks high-speed parallel links line extenders intrarack/subrack dense digital cross- interconnects connects max3831/max3832 +3.3v, 2.5gbps, sdh/sonet, 4-channel interconnect mux/demux ics with clock generator ________________________________________________________________ maxim integrated products 1 19-1534; rev 1; 10/99 ttl lvds lvds lvds 4 4 4 4 ttl ttl ttl ttl 2.5gbps cdr cmos overhead 2.5gbps optical transceiver ttl cml cml gnd trien +3.3v 0.33 f 0.1 f v cc fil+ fil- pdi1+ to pdi4+ pdi1- to pdi4- pdo1+ to pdo4+ pdo1- to pdo4- pclko+ pclko- sclki- sclki+ sdi- sdi+ sdo+ sdo- max3831 max3832 max3876 lvds rclki+ rclki- rsetes lben rsetfr test lof plben 155mhz ref clock input ttl typical application circuit ordering information part max3831 ucb max3832 ucb 0? to +85? 0? to +85? temp. range pin-package 64 tqfp-ep 64 tqfp-ep pin configuration appears at end of data sheet.
max3831/max3832 +3.3v, 2.5gbps, sdh/sonet, 4-channel interconnect mux/demux ics with clock generator 2 _______________________________________________________________________________________ absolute maximum ratings dc electrical characteristics (v cc = +3.0v to +3.6v, lvds differential load = 100 ? ?%, cml load = 50 ? ?% to v cc , all ttl inputs are open, t a = 0? to +85?, unless otherwise noted. typical values are at t a = +25? and v cc = +3.3v.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. positive supply voltage (v cc )...............................-0.5v to +5.0v input voltage (lvds, ttl)..........................-0.5v to (v cc + 0.5v) cml input voltage ..........................(v cc - 0.8v) to (v cc + 0.5v) fil+, fil- voltage.......................................-0.5v to (v cc + 0.5v) ttl output voltage ....................................-0.5v to (v cc + 0.5v) lvds output voltage ..................................-0.5v to (v cc +0.5v) cml output currents..........................................................22ma continuous power dissipation (t a = +85?) (note 1) 64-pin tqfp-ep (derate 40.0mw/? above +85?) .........2.6w operating temperature range...............................0? to +85? storage temperature range .............................-60? to +150? lead temperature (soldering, 10sec) .............................+300? short outputs together (note 3) trien = v cc trien = gnd figure 1 lvds input, v os = 1.2v conditions v v cc - v cc + 0.6 0.4 v is single-ended input voltage range v v cc - 0.2 output common-mode voltage ? 85 100 115 differential output impedance mvp-p 640 800 1000 v odp-p differential output voltage ma 12 output current ? 80 120 differential output impedance m ? >1 mv ?5 ?? v os ? change in magnitude of output offset voltage for complementary states v 1.125 1.275 v os output offset voltage mv ?5 ?? v od ? change in magnitude of differential output voltage for complementary states ma 440 580 i cc supply current mv 250 400 ? v od ? differential output voltage v 0.925 v ol output voltage low v 1.475 v oh output voltage high ? 270 i os input common-mode current mv 0 2400 v in input voltage range mv -100 +100 v idth differential input threshold mv 90 v hyst threshold hysteresis ? 85 100 115 r in input impedance units min typ max symbol parameter figure 2 ? 85 100 115 differential input impedance mvp-p 400 1200 differential input voltage swing lvds inputs and outputs cml inputs and outputs note 1: based on empirical data from the max3831/max3832 evaluation kit. cml inputs and outputs open, lvds input v os = 1.2v (note 2) max3831 max3832 480 614
max3831/max3832 +3.3v, 2.5gbps, sdh/sonet, 4-channel interconnect mux/demux ics with clock generator _______________________________________________________________________________________ 3 dc electrical characteristics (continued) (v cc = +3.0v to +3.6v, lvds differential load = 100 ? ?%, cml load = 50 ? ?% to v cc , all ttl inputs are open, t a = 0? to +85?, unless otherwise noted. typical values are at t a = +25? and v cc = +3.3v.) ac electrical characteristics (v cc = +3.0v to +3.6v, lvds differential load = 100 ? ?%, cml load = 50 ? ?% to v cc , all ttl inputs are open, t a = 0? to +85?, unless otherwise noted. typical values are at t a = +25? and v cc = +3.3v.) (note 4) trien = gnd i ol = 2ma i oh = 20? v ih = 2.0v v il = 0 conditions k ? 6 output impedance v 0.4 v ol output voltage low v 2.4 v oh output voltage high v 2.0 v ih input voltage high v 0.8 v il input voltage low ? -250 -50 i ih input current high ? -550 -100 i il input current low units min typ max symbol parameter note 2: when test = gnd, the pattern generator will consume an additional 30ma. note 3: guaranteed by design and characterization. (note 7) (note 5) 20% to 80% conditions ps p-p 818 sdj serial-data output deterministic jitter ps rms 3.5 mbps 622.08 parallel input data rate ns ?.5 t es maximum parallel input skew gbps 2.48832 serial-data output rate ps 120 t r , t f serial-data output rise/fall time units min typ max symbol parameter figure 3 figure 3 mbps 622.08 pdo parallel-data output rate gbps 2.48832 serial-data input rate ps 100 t su serial-data setup time ps 100 t h serial-data hold time (note 6) ps p-p 40 srj serial-data output random jitter ttl inputs and outputs max3831 pclko parallel-clock output frequency mhz 622.08 max3831, figure 3 t clk-q pclko to pdo_ delay ps -100 90 300 any differential pair t skew1 lvds differential skew ps 65 pdo1 to pdo4 t skew2 lvds channel-to-channel skew ps <100 lvds three-state enable time ns 30 note 4: ac characteristics are guaranteed by design and characterization. note 5: relative to the positive edge of the 155mhz reference clock. pdi1 to pdi4 aligned to rclki at reset. note 6: measured with a reference clock jitter of <1ps rms . note 7: deterministic jitter is the arithmetic sum of pattern-dependent jitter and pulse-width distortion. max3832 155.52 20% to 80% lvds output rise/fall time ps 350 4:1 multiplexer with clock generator 1:4 demultiplexer
max3831/max3832 +3.3v, 2.5gbps, sdh/sonet, 4-channel interconnect mux/demux ics with clock generator 4 _______________________________________________________________________________________ single-ended output | v od | v od v pdo- v oh v os v odp-p = v pdo+ - v pdo- -v od +v od 0v 0v (diff) v ol v pdo+ differential output d pdo+ r l = 100 ? pdo- v figure 1. definition of the lvds output sdi+ sdi- v id (sdi+) - (sdi-) 400mvp-p min 1200mvp-p max 200mv min 600mv max figure 2. definition of the cml input sclki sdi pclko pdo1?do4 note: signal shown is differential. for example, sclki = (sclki+) - (sclki-). t sclk = 1 / f sclk t su t clk-q t h figure 3. timing parameters
max3831/max3832 +3.3v, 2.5gbps, sdh/sonet, 4-channel interconnect mux/demux ics with clock generator _______________________________________________________________________________________ 5 serial-data output eye diagram max3831/2 toc01 50ps/div 2 23 -1 prbs pattern serial-data output jitter max3831/2 toc02 5ps/div wideband rms jitter = 2.48ps 0 200 100 400 300 500 600 -50 0 25 -25 50 75 100 supply current vs. temperature max3831/2 toc03 temperature ( c) supply current (ma) max3832 max3831 -10 -6 -8 -2 -4 2 0 4 8 6 10 0 0.4 0.6 0.2 0.8 1.0 1.2 1.4 1.6 elastic store range max3831/2 toc04 data to rclki delay at reset (ns) variation of data delay after reset (ns) channel aligned to rclki error-free operation -20 20 0 60 40 80 100 -50 0 25 -25 50 75 100 serial-data hold time max3831/2 toc05 temperature ( c) hold time (ps) 20 0 60 40 80 100 -50 0 25 -25 50 75 100 serial-data setup time max3831/2 toc06 temperature ( c) setup time (ps) 0 100 50 200 150 250 300 -50 0 25 -25 50 75 100 max3831 parallel clock-to-data output propagation delay vs. temperature max3831/2 toc07 temperature ( c) pclko to pdo_ propagation delay (ps) typical operating characteristics (v cc = +3.3v, t a = +25?, unless otherwise noted.)
max3831/max3832 +3.3v, 2.5gbps, sdh/sonet, 4-channel interconnect mux/demux ics with clock generator 6 _______________________________________________________________________________________ 7 self-test enable. when this ttl input is forced low, the built-in pattern generator generates a standard oc-12 sonet-like frame of 12 a1s, 12 a2s, and 9696 bytes of 2 7 - 1 pseudo- random bits. this also enables an internal serial-system-loopback path. the cml inputs (sdi and the sclk? and the lvds inputs are ignored in this mode. an internal 15k ? pull- up resistor pulls test high for normal operation. test 9 8 positive cml serial-data input, 2.488gbps sdi+ negative cml serial-data input, 2.488gbps sdi- 12 11 positive cml serial-clock input, 2.488ghz sclki+ negative cml serial-clock input, 2.488ghz sclki- 15 14 negative lvds parallel-clock output, 622.08mhz (max3831); 155.52mhz (max3832) pclko- positive lvds parallel-clock output, 622.08mhz (max3831); 155.52mhz (max3832) pclko+ 30 18 23, 26, 27 no connection n.c. frame reset. when this ttl input is forced low, the frame detector and pattern generator are reset. the lof output is also asserted low. an internal 15k ? pull-up resistor pulls rsetfr high for normal operation. rsetfr 33 31 ttl loss-of-frame output. asserts low in a loss-of-frame condition. lof 3-state enable. when this ttl input is forced low, all ttl and lvds outputs go into a high- impedance state. an internal 15k ? pull-up resistor pulls trien high for normal operation. trien 35, 37, 40, 42 34, 36, 39, 41 negative lvds parallel-data output, 622mbps pdo4- to pdo1- positive lvds parallel-data output, 622mbps pdo4+ to pdo1+ 45, 47, 51, 53 44, 46, 50, 52 negative lvds parallel-data input, 622mbps pdi4- to pdi1- positive lvds parallel-data input, 622mbps pdi4+ to pdi1+ 54 parallel system loopback enable. when this ttl input is forced low, the lvds parallel inputs route through the elastic store to the lvds parallel outputs. this bypasses the high- speed mux and demux. an internal 15k ? pull-up resistor pulls plben high for normal oper- ation. plben pin function name 6 line loopback enable. when this ttl input is forced low, the cml serial-data inputs (sdi? route directly to the cml serial-data outputs (sdo?. no other inputs or outputs are affected. an internal 15k ? pull-up resistor pulls lben high for normal operation. see test loopbacks . lben 4 positive cml serial-data output, 2.488gbps sdo+ 3 negative cml serial-data output, 2.488gbps sdo- 2, 5, 10, 13, 17, 24, 38, 55, 59, 64 +3.3v supply voltage v cc 1, 16, 25, 28, 29, 32, 43, 48, 49, 60, 63 supply ground gnd pin description 56 negative lvds reference clock input, 155.52mhz rclki- 57 positive lvds reference clock input, 155.52mhz rclki+
_______________detailed description the max3831/max3832 use a 4:1 mux and 1:4 demux with an elastic store buffer to simplify sdh/sonet interconnect i/o routing. the 622mbps low-voltage dif- ferential signal (lvds) parallel inputs pass through the 10-bit elastic store buffer, which accommodates ?.5ns skew on any single input relative to the 155mhz refer- ence clock input rclki. this reference clock is required to synthesize the internal 2.488ghz clock used to drive the elastic store and 4:1 multiplexer. all ttl and lvds outputs can be placed in a high-imped- ance state. see figure 4 for a functional diagram. the 4:1 mux bit-interleaves the parallel data, providing a 2.488gbps cml serial output to the optical or electri- cal driver. the cml serial input receives the 2.488gbps data, the demux deinterleaves it to 622mbps and sends the data to the frame detector. the frame detector monitors one 622mbps channel and rolls the demux into the proper channel assignment. the max3831/max3832 include high-speed, built-in self-test (bist), which also allows testing of the 622mbps parallel-system loopback and the 2.488gbps line loopback. elastic store buffer each parallel-data input, pdi1 to pdi4, passes through its respective 10-bit elastic store buffer. following an elastic store reset, this buffer accommodates ?.5ns of skew on any input relative to the 155mhz reference clock. figure 5 illustrates the elastic store buffer rela- tionship with rclki. the elastic store range graph in the typical operating characteristics shows the amount of data skew tolerated. following a 10? power-up period, the locations of the individual data-channel bit transitions are acquired, guaranteeing data preservation. the output of this block passes directly into the 4:1 mux. after power-up, the elastic store buffer must be reset by applying a low pulse on rsetes for at least 10ns. due to the inherent uncertainty of the data transitions between the parallel-data inputs there is no bit or frame alignment between these inputs. however, the demux ensures proper channel assignment is maintained. bit-interleaved multiplexer/ demultiplexer the max3831/max3832 use a bit interleave/deinterleave mux/demux. to guarantee channel assignment, one of the four channels is inverted before multiplexing to pro- vide a reference for the frame detector during demulti- plexing. after demultiplexing, the same channel is inverted back to the original data format. frame detector after a 2.5gbps serial data is bit deinterleaved into four 622mbps channels, an sdh/sonet frame detector monitors the fourth channel, looking for the 32-bit pat- tern (a1a1a2a2) in the oc-12 header. to maintain cor- rect channel assignment, the demux outputs rotate until this 32-bit overhead pattern is reliably detected. a loss- of-frame output, lof , indicates when the received data is in or out of frame. when lof goes high, the frame pattern is detected and the demux outputs are correct- ly assigned. when lof is low, the frame detection cir- cuitry is searching for the correct frame. a rsetfr (ttl, active low) is included to reset the frame detector when necessary. the frame detector uses an algorithm to detect an in- frame condition and a loss-of-frame condition; this algo- rithm is implemented to meet the sonet in-frame and false-frame specs. the frame_search state will occur upon start-up or reset. in this state, the frame detector scans through the incoming serial data searching for the framing pattern in the channel 4 output of the demux. while in this state, if the framing pattern is not found within 250?, the demux channels are shifted (rolled) and the frame search continues (figure 6). in-frame will be declared if two consecutive framing patterns are found at the correct byte locations within the sonet frame (9720 bytes). if this pattern is not pre- max3831/max3832 +3.3v, 2.5gbps, sdh/sonet, 4-channel interconnect mux/demux ics with clock generator _______________________________________________________________________________________________________ 7 pin description (continued) pin function name 58 elastic store reset. the elastic buffer is centered on a rising edge of rsetes , maximizing the elastic store range. data must be present for 10? before applying a pulse of at least 10ns. an internal 15k ? pull-up resistor pulls rsetes high for normal operation. rsetes 62 61 negative pll filter capacitor input. connect a 0.33? capacitor between fil+ and fil-. fil- positive pll filter capacitor input. connect a 0.33? capacitor between fil+ and fil-. fil+ ep ground. this must be soldered to a circuit board for proper thermal performance (see package information ). exposed paddle
max3831/max3832 sent at the correct location (false frame), the state machine will return to the frame_search state described above. while in the in_frame state, each frame will be checked for a framing pattern at the correct location. four consecutive false frames will cause the state machine to return to the frame_search state described above. the false-frame counter is reset with three or fewer consecutive false frames. built-in self-test with on-chip serial loopback an on-chip pattern generator can be enabled to pro- duce a 622mbps sdh/sonet-like transport overhead followed by a pseudorandom bit sequence. this consists of 12 a1s, 12 a2s, and a pseudorandom bit stream (prbs = 2 7 - 1). when test is low, this pattern is distrib- uted to all parallel inputs, bypassing the lvds input buffers. note, this pattern is skewed by one 622mhz +3.3v, 2.5gbps, sdh/sonet, 4-channel interconnect mux/demux ics with clock generator data input a0 a0 pdi1 pdi2 pdi3 pdi4 10ns -t es +t es rclki pdi1 pdi2 pdi3 pdi4 b1 b1 c0 c0 d1 d1 a0 b1 c0 d1 a1 a0 a1 b2 b0 b1 b2 c0 c1 d0 d1 c1 d0 data output of elastic store at t = t o data output of elastic store at t > t o rsetes figure 5. example of elastic store function 8 _______________________________________________________________________________________ (155mhz) rclki+ rclki- pdi1+ pdi1- pdi2+ pdi2- pdi3+ pdi3- pdi4+ pdi4- pdo1+ pdo1- pdo2+ pdo2- pdo3+ pdo3- pdo4+ pdo4- pclko+ pclko- rsetfr frame detector clock generator lof 622mhz 2.488ghz 2.488gbps sdo+ sdo- sdi+ sdi- sclki+ sclki- line loopback 2.488gbps system loopback rotate ck es es es es fil- fil+ 2.488ghz 155mhz 622mhz d ck 4:1 mux frequency generator *max3831: f pclko = 622mhz, max3832: f pclko = 155mhz lvds lvds lvds lvds lvds lvds lvds lvds lvds lvds trien lben test 622mbps parallel loopback 1:4 demux test rsetes pattern generator plben * max3831 max3832 figure 4. functional diagram
max3831/max3832 +3.3v, 2.5gbps, sdh/sonet, 4-channel interconnect mux/demux ics with clock generator _______________________________________________________________________________________ 9 frame detect start-up or reset start 250 s timer frame_search lof = 0 frame pattern detected? 1 frame detected reset byte and frame frame pattern detected? in_frame frame pattern detected? frame pattern detected? frame pattern detected? frame pattern detected? timer timed out? roll data no no no no no no no yes yes yes yes yes yes yes lof = 1 figure 6. frame detection flow diagram
max3831/max3832 +3.3v, 2.5gbps, sdh/sonet, 4-channel interconnect mux/demux ics with clock generator 10 ______________________________________________________________________________________ clock cycle between each channel. in this test mode, ser- ial data is internally looped back to the demux. all frame detect logic is exercised using this mode. the cml inputs (sdi and sclki? and lvds inputs (pdi_? are ignored in this mode. after the bist mode is enabled, the loss-of-frame flag lof goes high, indicating that the self- test has passed. in normal operation, test is left open (internally pulled high), disabling the pattern generator and accepting data from the parallel input channels. test loopbacks two additional test loopbacks are provided: parallel system loopback and serial line loopback. parallel system loopback in parallel system loopback, four 622mbps parallel input channels are phase aligned by an associated 10- bit elastic store and routed to the output lvds buffers. this loopback is controlled by setting plben low. normal data transmission is resumed when plben goes high (internally pulled high). serial line loopback serial line loopback is used for testing the performance of the optical transceiver and the transmission link. the received 2.488gbps data stream is routed to the trans- mit cml output buffer. line loopback is enabled when lben is asserted low. when lben is left open (internally pulled high), normal serial-data transmission resumes. lvds parallel interface the max3831 parallel interface includes four oc-12 data inputs, a 155mhz reference clock input, four 622mbps parallel-data outputs, and a 622mhz parallel- clock output (max3832, f pclko = 155mhz). all parallel inputs and outputs are lvds compatible to minimize power dissipation, speed transition time, and improve noise immunity. the 155mhz input signal at rclki requires a duty cycle between 40% and 60%. the lvds outputs go into a high-impedance state when trien is forced low. this simplifies system checks by allowing vectors to be forced on the lvds outputs. cml serial interface the max3831/max3832 provide a 2.488gbps serial- data stream to a driver and accept 2.488gbps serial data and a 2.488ghz clock signal from an external clock and data recovery device (max3876). the high- speed interface is cml compatible, resulting in lower system power dissipation and excellent performance (figure 7). __________applications information low-voltage differential signal inputs/outputs the max3831/max3832 have lvds inputs and outputs for interfacing with high-speed digital circuitry. all lvds inputs and outputs are compatible with the ieee-1596.3 lvds specification. this technology uses 250mv to 400mv differential low-voltage amplitudes to achieve fast transition times, minimize power dissipation, and improve noise immunity. for proper operation, the parallel clock and data lvds outputs (pclko+, pclko-, pdo_+, pdo_-) require 100 ? differential dc termination between the inverting and noninverting outputs. do not terminate these out- puts to ground. the parallel-data lvds inputs (pdi_+, pdi_-) are internally terminated with 100 ? differential input resistance and therefore do not require external termination. interfacing with pecl/ecl input levels when interfacing with differential pecl input levels, it is important to attenuate the signal while still maintaining 50 ? termination (figures 8 and 9). observe the com- mon-mode input voltage specifications. ac-coupling is required if a v cc other than 3.3v is used to maintain the input common-mode level (figure 8). max3831 max3832 max3876 50 ? 50 ? 50 ? 50 ? v cc v cc sdi+ sdi- sdo+ sdo- figure 7. cml-to-cml interface
max3831/max3832 +3.3v, 2.5gbps, sdh/sonet, 4-channel interconnect mux/demux ics with clock generator ______________________________________________________________________________________ 11 max3831 max3832 50 ? 50 ? v cc 100 ? pecl levels sdi+ 25 ? 25 ? *select r t such that the correct pecl common-mode level is achieved (typical pecl output current = 14ma). r t * 0.1 f 0.1 f sdi- r t * max3831 max3832 50 ? 50 ? 82 ? 82 ? 82 ? 82 ? v cc = 3.3v v cc = 3.3v pecl output sdi+ sdi- figure 8. pecl-to-cml interface figure 9. direct coupling of a pecl output into the max3831/ max3832 layout techniques for best performance, use good high-frequency layout techniques. filter voltage supplies, keep ground con- nections short, and use multiple vias where possible. use controlled-impedance transmission lines to inter- face with the max3831/max3832 high-speed inputs and outputs. place power-supply decoupling as close to v cc as possible. to reduce feedthrough, take care to isolate the input signals from the output signals.
max3831/max3832 +3.3v, 2.5gbps, sdh/sonet, 4-channel interconnect mux/demux ics with clock generator 12 ______________________________________________________________________________________ pin configuration 58 59 60 61 62 54 55 56 57 63 38 39 40 41 42 43 44 45 46 47 sclki+ n.c. gnd tqfp-ep top view fil+ fil- gnd v cc rclki+ rclki- v cc 52 53 49 50 51 pdi1+ pdi1- pdi2+ pdi2- gnd n.c. n.c. n.c. n.c. n.c. gnd v cc n.c. n.c. gnd gnd gnd pdi3+ pdi3- pdi4+ pdi4- gnd pdo1+ pdo1- pdo2+ pdo2- v cc 33 34 35 36 37 pdo3+ pdo3- pdo4+ pdo4- v cc sdi- sdi+ gnd pclko+ pclko- v cc sclki- v cc sdo+ sdo- v cc 48 gnd gnd 64 v cc v cc 23 22 21 20 19 27 26 25 24 18 29 28 32 31 30 17 11 10 9 8 7 6 5 4 3 2 16 15 14 13 12 1 max3831 max3832 trien rsetfr rsetes lof test lben plben ___________________chip information transistor count: 14,134
max3831/max3832 +3.3v, 2.5gbps, sdh/sonet, 4-channel interconnect mux/demux ics with clock generator ______________________________________________________________________________________ 13 package information 64l, tqfp.eps
max3831/max3832 +3.3v, 2.5gbps, sdh/sonet, 4-channel interconnect mux/demux ics with clock generator 14 ______________________________________________________________________________________ package information (continued)
max3831/max3832 +3.3v, 2.5gbps, sdh/sonet, 4-channel interconnect mux/demux ics with clock generator ______________________________________________________________________________________ 15 notes
max3831/max3832 +3.3v, 2.5gbps, sdh/sonet, 4-channel interconnect mux/demux ics with clock generator maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 16 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 1999 maxim integrated products printed usa is a registered trademark of maxim integrated products. notes
e nglish ? ???? ? ??? ? ??? what's ne w p roducts solutions de sign ap p note s sup p ort buy comp any me mbe rs max3831 part number table notes: see the max3831 quickview data sheet for further information on this product family or download the max3831 full data sheet (pdf, 296kb). 1. other options and links for purchasing parts are listed at: http://www.maxim-ic.com/sales . 2. didn't find what you need? ask our applications engineers. expert assistance in finding parts, usually within one business day. 3. part number suffixes: t or t&r = tape and reel; + = rohs/lead-free; # = rohs/lead-exempt. more: see full data sheet or part naming c onventions . 4. * some packages have variations, listed on the drawing. "pkgc ode/variation" tells which variation the product uses. 5. part number free sample buy direct package: type pins size drawing code/var * temp rohs/lead-free? materials analysis max3831uc b-d tqfp;64 pin;10x10x1 mm dwg: 21-0084c (pdf) use pkgcode/variation: c 64e-3 * 0c to +85c rohs/lead-free: no materials analysis max3831uc b-td tqfp;64 pin;10x10x1 mm dwg: 21-0084c (pdf) use pkgcode/variation: c 64e-3 * 0c to +85c rohs/lead-free: no materials analysis didn't find what you need? c ontac t us: send us an email c opyright 2 0 0 7 by m axim i ntegrated p roduc ts , dallas semic onduc tor ? legal n otic es ? p rivac y p olic y

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